1. Field of the Invention
This invention relates in general to a pin-assignment method for integrated circuit (IC) packages, which can allow an increase in the electro-static discharge (ESD) protective capability for the IC chip packed in the IC package. Specifically, the pin-assignment method organizes the no-connect pins of the IC package into groups and then assigns each of the two pins that bound each no-connect pin group to be connected to a power line, whereby the IC chip can be increased in its ESD protective capability and simplified in its wiring complexity.
2. Description of Related Art
Electrostatic discharge (ESD) is a movement of static electricity from a nonconductive surface, which usually causes damage to the semiconductors and various other circuit components in IC chips. A person walking on a carpet, for instance, can carry an amount of electrostatic charge up to several thousands of volts under high relative humidity (RH) conditions and over 10,000 volts under low relative humidity conditions. If such a person touches an IC chip by hand, the electrostaticity on his/her body would instantaneously be discharged to the IC chip, thus causing damage to the IC chip. The ESD damage is particularly common and severe on CMOS (complementary metal-oxide semiconductor) IC devices.
To protect IC chips against ESD damage, various solutions have been proposed. One solution suggests the provision of an ESD protective circuit between the internal circuit of the IC chip and each of the bonding pads. FIG. 1 shows a conventional pin-assignment method used on an IC package. As shown, the IC package includes an IC chip on which an internal circuit 20 and a plurality of bonding pads 11, 13, 15 are formed. Further, the IC package includes a plurality of pins 10, 12, 14, 16, 17, 18, 19 on the periphery thereof, of which the pin 10 is a power pin (i.e., VDD or VSS pin) which is internally connected via a bonding wire 100 to the bonding pad 11; the pin 12 is an I/O pin which is internally connected via a bonding wire 120 to the bonding pad 13; the pin 14 is an input pin which is internally connected via a bonding wire 140 to the bonding pad 15; and the other pins 16, 17, 18, 19 are not in use (not wired) and thus are referred to as “no-connect pins”. To prevent ESD current from flowing via the bonding pads 11, 13, 15 into the internal circuit, each of the bonding pads 11, 13, 15 is connected to a ESD protective circuit (not shown).
A trend in IC packaging is to provide a larger number of pins on a single package so as to achieve the purpose of a high packing density of pins on the IC package. Since the IC package is very small in size, the increased number of pins will cause the gap (i.e., the pitch) between two adjacent pins, as indicated by the reference numeral G in FIG. 1 between the pins 14 and 19, to be further reduced. The reduction of the pin gap, however, causes a new problem in ESD protection for the IC package. This problem is described in a paper entitled “New Failure Mechanism due to No-Connect Pin ESD Stressing” which is authored by Matsumoto et al. and published in 1994 EOS/ESD Symposium, pp. 90-95. This paper reveals the fact that, when a human body model (HBM) ESD pulse is repeatedly applied to a certain no-connect pin on the IC package, any of its two neighboring pins, if wired to the internal circuit, would become particularly vulnerable to ESD damage. This is because that the electrostatic charge will accumulate in the resin around the no-connect pin, thus resulting in a large potential difference between the no-connect pin and its neighboring pins, thus significantly reducing the ESD resistant capability of the neighboring pins.
Taking the IC package of FIG. 1 as an example, assume that the input pin 14 is able to withstand a maximum of ESD stress of 3 kV (kilovolt), then when an ESD stress of 1.5 kV is applied to the no-connect pin 19, the electrostatic charge therefrom will accumulate in the resin around the no-connect pin 19, eventually resulting in a large potential difference between the no-connect pin 19 and its neighboring pins (i.e., 14, 18). When this potential reaches a large enough level, it would cause a sudden ESD current to flow through the gap G to the neighboring pin 14. Said ESD current will then flow from the pin 14 via the bonding wire 140 and the bonding pad 15 to the internal circuit, whereby an ESD damage could occur. In short, when an ESD stress of 3 kV is being applied to the pin 14, the internal circuit of the IC chip wired to the pin 14 would not be damaged thereby; however, the application of an ESD stress of 1.5 kV to the no-connect pin 19 would cause ESD damage to the internal circuit wired to the neighboring pin 14.
Early types of IC packages have only a small number of pins thereon, so the above-mentioned proximity problem that would cause ESD damage is unobvious. However, newer types of IC packages, such as QFP (quad flat packages), MQFP, TQFP, etc., usually come with more than one hundred pins that are packed in plastic or resin compounds. With such a large number of pins on a small-size IC package, the above-mentioned proximity problem becomes a serious consideration. One conventional solution to this problem is to increase the ESD protective capability of the input and I/O pins of the IC package to a higher level, for example from 2 kV to 4-5 kV. This scheme can protect the input and I/O pins of the IC package against ESD damage when any of its neighboring no-connect pins is subjected to an ESD stress of 2 kV. One drawback to this solution, however, is that the ESD protective circuitry needed to provide such an ESD protective capability will take up more area on the IC chip, thus increasing the chip size.
On an IC package, those pins that are electrically and functionally engaged, such as input pins, output pins, I/O pins, and power pins, are referred to as active pins. Each active pin is electrically wired to a bonding pad and an ESD protective circuit. Typically, the circuit connected to the power buses on the IC chip has the highest ESD protective capability since the power pins are connected to the power bus VDD or VSS. In addition to its high ESD capacity, each power bus has a capacitance of from 1 nF (nanofarad) to 10 nF formed between the N-well and P-well, or between the N-well and the substrate of the IC chip, which can absorb a great amount of charges from ESD. The input pins, I/O pins and output pins are inferior to the power pins in ESD protective capability.
FIGS. 2A and 2B are schematic diagrams used to depict two conventional pin-assignment methods used for pin assignment on IC packages.
Referring to FIG. 2A, the IC package shown here includes an IC chip 58 having a plurality of bonding pads 42, 44, 46, 48 formed thereon. Further, the IC-package includes a plurality of pins 30, 32, 34, 36, 38, 40, which are respectively assigned as a VSS power pin, an input pin, a first no-connect pin, a VDD power pin, a second no-connect pin, and an I/O pin. The VSS power pin 30, the input pin 32, the VDD power pin 36, and the I/O pin 40 are wired respectively via a plurality of bonding wires 50, 52, 54, 56 to the bonding pads 42, 44, 46, 48; while the first and second no-connect pins 34, 38 are unwired. Via the bonding pads 42, 44, 46, 48, these active pins (i.e., 30, 32, 36, 40) are functionally connected to the internal circuit of the IC chip 58.
Referring to FIG. 2B, the IC package shown here includes an IC chip 88 having a plurality of bonding pads 72, 74, 76, 78 formed thereon. Further, the IC package includes a plurality of pins 60, 62, 64, 66, 68, 70, which are respectively assigned as a VSS power pin, an input pin, a first no-connect pin, a second no-connect pin, an I/O pin, and a VDD power pin. The VSS power pin 60, the input pin 62, the I/O pin 68, and the VDD power pin 70 are wired respectively via a plurality of bonding wires 80, 82, 84, 86 to the bonding pads 72, 74, 76, 78; while the first and second no-connect pins 64, 66 are unwired. Via the bonding pads 72, 74, 76, 78, these active pins (i.e., 60, 62, 68, 70) are functionally connected to the internal circuit of the IC chip 88.
It can be seen from FIGS. 2A and 2B that, by the conventional pin-assignment methods, the no-connect pins are arranged arbitrarily; in the case of FIG. 2A, for example, the no-connect pins are arranged next to the input pin, the VDD power pin, and the I/O pin; while in the case of FIG. 2B, the no-connect pins are arranged next to the input pin and the I/O pin. These pin-assignment methods take no consideration of ESD protections. Therefore, when these pin-assignment methods are utilized on IC packages with a high density of pins, the arrangement of the no-connect pins next to ESD-sensitive pins could cause the problem of ESD damage.